1. Field of the Invention
This invention relates to a clock switching circuit which performs switching of multiple-phase clock signals, and in particular relates to a clock switching circuit which enables reduction of power consumption.
2. Description of the Related Art
A clock switching circuit of this invention selects one clock signal from a plurality of clock signals of the same frequency with different phases, and, by repeated switching to the adjacent-phase clock signal, selects a desired clock signal. In the receivers of communication systems and the data reproduction devices of hard disk drives, one clock signal is selected from a plurality of clock signals at the same frequency but having different phases, and the selected clock signal is used as the sampling clock signal in data sampling. For example, in Japanese Patent Laid-open No. 2001-56918, selection of and switching to a clock signal synchronized with the timing of a data pulse, from among multiple-phase clock signals, is disclosed.
A clock switching circuit has been proposed in which, in clock switching, by repeatedly switching to the adjacent-phase clock signal, the clock signal of the desired phase is selected. For example, such a circuit is disclosed in Japanese Patent Laid-open No. 2006-11704. In this clock switching circuit, when selecting one clock phase out of eight-phase clock, three layers of two-clock selectors are arranged in tournament form, and the selectors in each layer are controlled by three-bit selection signals. That is, four two-clock selectors to each of which clocks are input are provided in the first layer, two two-clock selectors to which the selector output of the first layer are input are provided in the second layer, and one two-clock selector to which the selector output of the second layer are input is provided in the third layer.
By using Gray codes for these selection signals, only one bit among the three-bit selection signals changes, and so switching to the adjacent-phase signal is possible. When switching the clock signal, only one bit is changed in the three-bit selection signals (from 0 to 1 or from 1 to 0), so that the problem of skew between selection signals can be resolved, and the occurrence of glitches in the output clock during clock switching is prevented.
In each selector is provided a flip-flop circuit which latches the selection signal in the interval in which two input clock signals are at the same level (H level or L level), and one of the input clock signals is selected according to the output of the flip-flop circuit. Hence selectors in the clock switching circuit perform switching in intervals in which the two input clock signals are at the same level, so that there is no fluctuation in the output clock level, and glitches do not occur.